JP-2005-268336-A discloses a semiconductor device in which a diffusion region is provided around a boundary between an SOI (Silicon on Insulator) region and a non-SOI region, and field isolation regions are provided on both sides of the diffusion region. The field isolation region is not provided around the boundary, thereby preventing a void from being generated.
JP-2006-80492-A discloses a semiconductor device in which a depth of a device isolation groove in a memory cell region is set smaller than a depth of a device isolation groove in a peripheral circuit region, thereby uniforming a height of the device isolation region in the memory cell region and the peripheral circuit region. Since a step of STI (Shallow Trench Isolation) is relaxed, a conductive film is prevented from being remained against etching, and a lower film is prevented from being excessively etched.
JP-2007-13074-A discloses a method for manufacturing a semiconductor device in which a depth of an element isolating trench in a cell region is formed smaller than a depth of an element isolating trench in a peripheral region, thereby preventing a thinning phenomenon of a gate oxide film in the peripheral region and a hump phenomenon that leak current flows into a low-voltage element.
JP-2006-41397-A discloses a method for manufacturing a semiconductor device by uniforming the heights of element isolation regions from the surface of a semiconductor substrate, when an insulating film is buried in different depth grooves to form the element isolation regions.